Vol. 3C 35-199

MODEL-SPECIFIC REGISTERS (MSRS)

16

PROCHOT Log 
When set, indicates that the PROCHOT Status bit has asserted 

since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

17

Thermal Log 
When set, indicates that the Thermal Status bit has asserted 

since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

19:18

Reserved.

20

Graphics Driver Log 
When set, indicates that the Graphics Driver Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

21

Autonomous Utilization-Based Frequency Control Log 
When set, indicates that the Autonomous Utilization-Based 

Frequency Control Status bit has asserted since the log bit was 

last cleared.
This log bit will remain set until cleared by software writing 0.

22

VR Therm Alert Log 
When set, indicates that the VR Therm Alert Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

23

Reserved.

24

Electrical Design Point Log 
When set, indicates that the EDP Status bit has asserted since the 

log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

25

Core Power Limiting Log 
When set, indicates that the Core Power Limiting Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

26

Package-Level PL1 Power Limiting Log 
When set, indicates that the Package Level PL1 Power Limiting 

Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

27

Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting 

Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

28

Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has 

asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.

Table 35-28.  MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec