35-178 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

2:0

Package C-State Limit (R/W) 
Specifies the lowest processor-specific C-state code name 

(consuming the least power). for the package. The default is set as 

factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

10

I/O MWAIT Redirection Enable (R/W) 
When set, will map IO_read instructions sent to IO register 

specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions

14:11

Reserved.

15

CFG Lock (R/WO) 
When set, lock bits 15:0 of this register until next reset.

63:16

Reserved.

179H

377

IA32_MCG_CAP

Thread

Global Machine Check Capability (R/O)

7:0

Count

8

MCG_CTL_P

9

MCG_EXT_P

10

MCP_CMCI_P

11

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

24

MCG_SER_P

25

Reserved.

26

MCG_ELOG_P

63:27

Reserved.

17FH

383

MSR_ERROR_CONTROL

Package

MC Bank Error Configuration (R/W)

0

Reserved

1

MemError Log Enable (R/W) 
When set, enables IMC status bank to log additional info in bits 

36:32.

63:2

Reserved.

Table 35-24.  MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E 

microarchitecture) (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec