35-154 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

7

Core

Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)

31:8

Reserved.

32

Thread

Set 1 to clear Ovf_FixedCtr0 

33

Thread

Set 1 to clear Ovf_FixedCtr1 

34

Thread

Set 1 to clear Ovf_FixedCtr2 

60:35

Reserved.

61

Thread

Set 1 to clear Ovf_Uncore 

62

Thread

Set 1 to clear Ovf_BufDSSAVE 

63

Thread

Set 1 to clear CondChgd 

3F1H

1009

MSR_PEBS_ENABLE

Thread

See Section 18.7.1.1, “Precise Event Based Sampling (PEBS).”

0

Enable PEBS on IA32_PMC0. (R/W)

1

Enable PEBS on IA32_PMC1. (R/W)

2

Enable PEBS on IA32_PMC2. (R/W)

3

Enable PEBS on IA32_PMC3. (R/W)

31:4

Reserved.

32

Enable Load Latency on IA32_PMC0. (R/W)

33

Enable Load Latency on IA32_PMC1. (R/W)

34

Enable Load Latency on IA32_PMC2. (R/W)

35

Enable Load Latency on IA32_PMC3. (R/W)

62:36

Reserved.

63

Enable Precise Store. (R/W)

3F6H

1014

MSR_PEBS_LD_LAT

Thread

see See Section 18.7.1.2, “Load Latency Performance Monitoring 

Facility.”

15:0

Minimum threshold latency value of tagged load operation that will 

be counted. (R/W)

63:36

Reserved.

3F8H

1016

MSR_PKG_C3_RESIDENCY

Package

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

Package C3 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C3 

states. Count at the same frequency as the TSC.

3F9H

1017

MSR_PKG_C6_RESIDENCY

Package

Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.

63:0

Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6 

states. Count at the same frequency as the TSC.

Table 35-18.  MSRs Supported by Intel® Processors 

based on Intel® microarchitecture code name Sandy Bridge (Contd.)

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec