35-44 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

1

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W. 

2

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W. 

3

MCERR# Drive Enable (R/W) 
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W. 

4

Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled
Note: Not all processor implements R/W. 

5

Reserved.

6

Reserved.

7

BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled 
Note: Not all processor implements R/W. 

8

Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled 

9

Execute BIST (R/O)
1 = Enabled; 0 = Disabled 

10

MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled

11

Intel TXT Capable Chipset. (R/O)
1 = Present; 0 = Not Present

12

BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled 

13

Reserved.

14

1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes

15

Reserved.

17:16

APIC Cluster ID (R/O)

18

N/2 Non-Integer Bus Ratio (R/O)
0 = Integer ratio; 1 = Non-integer ratio

19

Reserved.

21: 20

Symmetric Arbitration ID (R/O)

26:22

Integer Bus Frequency Ratio (R/O)

Table 35-3.  MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec