Vol. 3C 35-25

MODEL-SPECIFIC REGISTERS (MSRS)

63

Set to 1to clear CondChgd: bit.

If CPUID.0AH: EAX[7:0] > 0

391H

913

IA32_PERF_GLOBAL_STATUS_SET

Global Performance Counter Overflow Set 

Control (R/W)

If CPUID.0AH: EAX[7:0] > 3

0

Set 1 to cause Ovf_PMC0 = 1.

If CPUID.0AH: EAX[7:0] > 3

1

Set 1 to cause Ovf_PMC1 = 1

If CPUID.0AH: EAX[15:8] > 

1

2

Set 1 to cause Ovf_PMC2 = 1

If CPUID.0AH: EAX[15:8] > 

2

n

Set 1 to cause Ovf_PMCn = 1

If CPUID.0AH: EAX[15:8] > 

n

31:n

Reserved.

32

Set 1 to cause Ovf_FIXED_CTR0 = 1.

If CPUID.0AH: EAX[7:0] > 3

33

Set 1 to cause Ovf_FIXED_CTR1 = 1.

If CPUID.0AH: EAX[7:0] > 3

34

Set 1 to cause Ovf_FIXED_CTR2 = 1.

If CPUID.0AH: EAX[7:0] > 3

54:35

Reserved.

55

Set 1 to cause Trace_ToPA_PMI = 1.

If CPUID.0AH: EAX[7:0] > 3

57:56

Reserved.

58

Set 1 to cause LBR_Frz = 1.

If CPUID.0AH: EAX[7:0] > 3

59

Set 1 to cause CTR_Frz = 1.

If CPUID.0AH: EAX[7:0] > 3

58

Set 1 to cause ASCI = 1.

If CPUID.0AH: EAX[7:0] > 3

61

Set 1 to cause Ovf_Uncore = 1.

If CPUID.0AH: EAX[7:0] > 3

62

Set 1 to cause OvfBuf = 1.

If CPUID.0AH: EAX[7:0] > 3

63

Reserved

392H

914

IA32_PERF_GLOBAL_INUSE

Indicator of core perfmon interface is in use 

(RO)

If CPUID.0AH: EAX[7:0] > 3

0

IA32_PERFEVTSEL0 in use

1

IA32_PERFEVTSEL1 in use

If CPUID.0AH: EAX[15:8] > 

1

2

IA32_PERFEVTSEL2 in use

If CPUID.0AH: EAX[15:8] > 

2

n

IA32_PERFEVTSELn in use

If CPUID.0AH: EAX[15:8] > 

n

31:n

Reserved.

32

IA32_FIXED_CTR0 in use

33

IA32_FIXED_CTR1 in use

34

IA32_FIXED_CTR2 in use

62:35

Reserved or Model specific.

63

PMI in use.

3F1H

1009

IA32_PEBS_ENABLE

PEBS Control (R/W)

Table 35-2.  IA-32 Architectural MSRs (Contd.)

Register 

Address

Architectural MSR Name and bit 

fields 

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal