Vol. 3C 35-23

MODEL-SPECIFIC REGISTERS (MSRS)

58

LBR_Frz: LBRs are frozen due to 
• IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1,

• The LBR stack overflowed

If CPUID.0AH: EAX[7:0] > 3

59

CTR_Frz: Performance counters in the core 

PMU are frozen due to 
• IA32_DEBUGCTL.FREEZE_PERFMON_ON_

PMI=1,

• one or more core PMU counters 

overflowed.

If CPUID.0AH: EAX[7:0] > 3

60

ASCI: Data in the performance counters in 

the core PMU may include contributions 

from the direct or indirect operation intel 

SGX to protect an enclave.

If CPUID.(EAX=07H, 

ECX=0):EBX[2] = 1

61

Ovf_Uncore: Uncore counter overflow 

status.

If CPUID.0AH: EAX[7:0] > 2

62

OvfBuf: DS SAVE area Buffer overflow 

status.

If CPUID.0AH: EAX[7:0] > 0

63

CondChgd

: status bits of this register has 

changed.

If CPUID.0AH: EAX[7:0] > 0

38FH

911

IA32_PERF_GLOBAL_CTRL 

Global Performance Counter Control (R/W)
Counter increments while the result of 

ANDing respective enable bit in this MSR 

with the corresponding OS or USR bits in 

the general-purpose or fixed counter 

control MSR is true.

If CPUID.0AH: EAX[7:0] > 0

0

EN_PMC0

If CPUID.0AH: EAX[15:8] > 

0

1

EN_PMC1

If CPUID.0AH: EAX[15:8] > 

1

2

EN_PMC2

If CPUID.0AH: EAX[15:8] > 

2

n

EN_PMCn

If CPUID.0AH: EAX[15:8] > 

n

31:n+1

Reserved.

32

EN_FIXED_CTR0

If CPUID.0AH: EDX[4:0] > 0

33

EN_FIXED_CTR1

If CPUID.0AH: EDX[4:0] > 1

34

EN_FIXED_CTR2

If CPUID.0AH: EDX[4:0] > 2

63:35

Reserved.

390H

912

IA32_PERF_GLOBAL_OVF_CTRL 

Global Performance Counter Overflow 

Control (R/W)

If CPUID.0AH: EAX[7:0] > 0 

&& CPUID.0AH: EAX[7:0] 

<= 3

0

Set 1 to Clear Ovf_PMC0 bit.

If CPUID.0AH: EAX[15:8] > 

0

1

Set 1 to Clear Ovf_PMC1 bit.

If CPUID.0AH: EAX[15:8] > 

1

Table 35-2.  IA-32 Architectural MSRs (Contd.)

Register 

Address

Architectural MSR Name and bit 

fields 

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal