Vol. 3C 35-21

MODEL-SPECIFIC REGISTERS (MSRS)

10

Fixed Range MTRR Enable 

11

MTRR Enable 

63:12

Reserved.

309H

777

IA32_FIXED_CTR0 

(MSR_PERF_FIXED_CTR0)

Fixed-Function Performance Counter 0 

(R/W): Counts Instr_Retired.Any.

If CPUID.0AH: EDX[4:0] > 0

30AH

778

IA32_FIXED_CTR1 

(MSR_PERF_FIXED_CTR1)

Fixed-Function Performance Counter 1 

(R/W): Counts CPU_CLK_Unhalted.Core

If CPUID.0AH: EDX[4:0] > 1

30BH

779

IA32_FIXED_CTR2 

(MSR_PERF_FIXED_CTR2)

Fixed-Function Performance Counter 2 

(R/W): Counts CPU_CLK_Unhalted.Ref

If CPUID.0AH: EDX[4:0] > 2

345H

837

IA32_PERF_CAPABILITIES

RO

If CPUID.01H: ECX[15] = 1

5:0

LBR format

6

PEBS  Trap

7

PEBSSaveArchRegs

11:8

PEBS Record Format

12

1: Freeze while SMM is supported.

13

1: Full width of counter writable via 

IA32_A_PMCx.

63:14

Reserved.

38DH

909

IA32_FIXED_CTR_CTRL Fixed-Function Performance Counter 

Control (R/W)
Counter increments while the results of 

ANDing respective enable bit in 

IA32_PERF_GLOBAL_CTRL with the 

corresponding OS or USR bits in this MSR is 

true.

If CPUID.0AH: EAX[7:0] > 1

0

EN0_OS: Enable Fixed Counter 0 to count 

while CPL = 0.

1

EN0_Usr: Enable Fixed Counter 0 to count 

while CPL > 0.

2

AnyThread: When set to 1, it enables 

counting the associated event conditions 

occurring across all logical processors 

sharing a processor core. When set to 0, the 

counter only increments the associated 

event conditions occurring in the logical 

processor which programmed the MSR.

If CPUID.0AH:
EAX[7:0] > 2

3

EN0_PMI:  Enable  PMI  when  fixed  counter  0 

overflows.

4

EN1_OS: Enable Fixed Counter 1to count 

while CPL = 0.

5

EN1_Usr: Enable Fixed Counter 1to count 

while CPL > 0.

Table 35-2.  IA-32 Architectural MSRs (Contd.)

Register 

Address

Architectural MSR Name and bit 

fields 

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal