35-12 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

11

Branch Trace Storage Unavailable (RO)
1 = Processor doesn’t support branch 

trace storage (BTS)

0 = BTS is supported

0F_0H

12

Processor Event Based Sampling (PEBS) 

Unavailable (RO) 
1 =  PEBS is not supported; 
0 =  PEBS is supported. 

06_0FH

15:13

Reserved.

16

Enhanced Intel SpeedStep Technology 

Enable (R/W)
0=  Enhanced Intel SpeedStep 

Technology disabled

1 =  Enhanced Intel SpeedStep 

Technology enabled

If CPUID.01H: ECX[7] =1

17

Reserved.

18

ENABLE MONITOR FSM (R/W)
When this bit is set to 0, the MONITOR 

feature flag is not set (CPUID.01H:ECX[bit 

3] = 0). This indicates that 

MONITOR/MWAIT are not supported. 
Software attempts to execute 

MONITOR/MWAIT will cause #UD when this 

bit is 0.
When this bit is set to 1 (default), 

MONITOR/MWAIT are supported 

(CPUID.01H:ECX[bit 3] = 1).
If the SSE3 feature flag ECX[0] is not set 

(CPUID.01H:ECX[bit 0] = 0), the OS must 

not attempt to alter this bit. BIOS must 

leave it in the default state. Writing this bit 

when the SSE3 feature flag is set to 0 may 

generate a #GP exception.

0F_03H

21:19

Reserved.

Table 35-2.  IA-32 Architectural MSRs (Contd.)

Register 

Address

Architectural MSR Name and bit 

fields 

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal