35-4 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

3AH

58

IA32_FEATURE_CONTROL

Control Features in Intel 64 Processor 

(R/W)

If any one enumeration 

condition for defined bit 

field holds

0

Lock bit (R/WO): (1 = locked). When set, 

locks this MSR from being written, writes 

to this bit will result in GP(0).
Note: Once the Lock bit is set, the contents 

of this register cannot be modified. 

Therefore the lock bit must be set after 

configuring support for Intel Virtualization 

Technology and prior to transferring control 

to an option ROM or the OS. Hence, once 

the Lock bit is set, the entire 

IA32_FEATURE_CONTROL contents are 

preserved across RESET when PWRGOOD is 

not deasserted.

If any one enumeration 

condition for defined bit 

field position greater than 

bit 0 holds

1

Enable VMX inside SMX operation (R/WL): 

This bit enables a system executive to use 

VMX in conjunction with SMX to support 

Intel® Trusted Execution Technology.
BIOS must set this bit only when the CPUID 

function 1 returns VMX feature flag and 

SMX feature flag set (ECX bits 5 and 6 

respectively).

If CPUID.01H:ECX[5] = 1 

&& CPUID.01H:ECX[6] = 1

2

Enable VMX outside SMX operation (R/WL): 

This bit enables VMX for system executive 

that do not require SMX.
BIOS must set this bit only when the CPUID 

function 1 returns VMX feature flag set 

(ECX bit 5).

If CPUID.01H:ECX[5] = 1 

7:3

Reserved

14:8

SENTER Local Function Enables (R/WL): 

When set, each bit in the field represents 

an enable control for a corresponding 

SENTER function. This bit is supported only 

if CPUID.1:ECX.[bit 6] is set

If CPUID.01H:ECX[6] = 1

15

SENTER Global Enable (R/WL): This bit must 

be set to enable SENTER leaf functions. 

This bit is supported only if 

CPUID.1:ECX.[bit 6] is set

If CPUID.01H:ECX[6] = 1

16

Reserved

17

SGX Launch Control Enable (R/WL): This bit 

must be set to enable runtime 

reconfiguration of SGX Launch Control via 

IA32_SGXLEPUBKEYHASHn MSR. 

If CPUID.(EAX=07H, 

ECX=0H): ECX[30] = 1

18

SGX Global Enable (R/WL): This bit must be 

set to enable SGX leaf functions. 

If CPUID.(EAX=07H, 

ECX=0H): EBX[2] = 1

19

Reserved

Table 35-2.  IA-32 Architectural MSRs (Contd.)

Register 

Address

Architectural MSR Name and bit 

fields 

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal