30-4 Vol. 3C

VMX INSTRUCTION REFERENCE

CASE INVEPT_TYPE OF

1:

// single-context invalidation

IF VM entry with the “enable EPT“ VM execution control set to 1
would fail due to the EPTP value

THEN VMfail(Invalid operand to INVEPT/INVVPID);
ELSE

Invalidate mappings associated with EPTP[51:12];
VMsucceed;

FI;
BREAK;

2:

// global invalidation

Invalidate mappings associated with all EPTPs;
VMsucceed;
BREAK;

ESAC;

FI;

FI;

Flags Affected

See the operation section and Section 30.2.

Protected Mode Exceptions

#GP(0)

If the current privilege level is not 0.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the source operand is located in an execute-only code segment.

#PF(fault-code)

If a page fault occurs in accessing the memory operand.

#SS(0)

If the memory operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.

#UD

If not in VMX operation.
If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0).
If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not 

support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0).

Real-Address Mode Exceptions

#UD

If executed outside VMX root operation.

Virtual-8086 Mode Exceptions

#UD

The INVEPT instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD

The INVEPT instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#GP(0)

If the current privilege level is not 0.
If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is 

in a non-canonical form.

#PF(fault-code)

If a page fault occurs in accessing the memory operand.

#SS(0)

If the memory operand is in the SS segment and the memory address is in a non-canonical 

form.