Vol. 3C 27-27

VM EXITS

If the processor supports the Intel 64 architecture and the processor supports N < 64 linear-address bits, 
each of bits 63:N is set to the value of bit N–1.

1

 The values loaded for base addresses for FS and GS are 

also manifest in the FS.base and GS.base MSRs.

— TR. Loaded from the host-state area. If the processor supports the Intel 64 architecture and the processor 

supports N < 64 linear-address bits, each of bits 63:N is set to the value of bit N–1.

•

The segment limit is set as follows:
— CS. Set to FFFFFFFFH (corresponding to a descriptor limit of FFFFFH and a G-bit setting of 1).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to FFFFFFFFH.
— TR. Set to 00000067H.

•

The type field and S bit are set as follows:
— CS. Type set to 11 and S set to 1 (execute/read, accessed, non-conforming code segment).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, type set to 3 and S set to 1 

(read/write, accessed, expand-up data segment).

— TR. Type set to 11 and S set to 0 (busy 32-bit task-state segment).

•

The DPL is set as follows:
— CS, SS, and TR. Set to 0. The current privilege level (CPL) will be 0 after the VM exit completes.
— DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 0.

•

The P bit is set as follows:
— CS, TR. Set to 1.
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.

•

On processors that support Intel 64 architecture, CS.L is loaded with the setting of the “host address-space 
size” VM-exit control. Because the value of this control is also loaded into IA32_EFER.LMA (see Section 27.5.1), 
no VM exit is ever to compatibility mode (which requires IA32_EFER.LMA = 1 and CS.L = 0).

•

D/B.
— CS. Loaded with the inverse of the setting of the “host address-space size” VM-exit control. For example, if 

that control is 0, indicating a 32-bit guest, CS.D/B is set to 1.

— SS. Set to 1.
— DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
— TR. Set to 0.

•

G.
— CS. Set to 1.
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to 1.
— TR. Set to 0.

The host-state area does not contain a selector field for LDTR. LDTR is established as follows on all VM exits: the 
selector is cleared to 0000H, the segment is marked unusable and is otherwise undefined (although the base 
address is always canonical).
The base addresses for GDTR and IDTR are loaded from the GDTR base-address field and the IDTR base-address 
field, respectively. If the processor supports the Intel 64 architecture and the processor supports N < 64 linear-
address bits, each of bits 63:N of each base address is set to the value of bit N–1 of that base address. The GDTR 
and IDTR limits are each set to FFFFH.

1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is 

returned in bits 15:8 of EAX.