Vol. 3C 27-17

VM EXITS

6:3

Reg1:

0 =  RAX

1 =  RCX

2 =  RDX

3 =  RBX

4 =  RSP

5 =  RBP

6 =  RSI

7 =  RDI

8–15 represent R8–R15, respectively (used only on processors that support Intel 64 architecture)

Undefined for memory instructions (bit 10 is clear).

9:7

Address size:

0: 16-bit

1: 32-bit

2: 64-bit (used only on processors that support Intel 64 architecture)

Other values not used. Undefined for register instructions (bit 10 is set).

10

Mem/Reg (0 = memory; 1 = register).

14:11

Undefined.

17:15

Segment register:

0: ES

1: CS

2: SS

3: DS

4: FS

5: GS

Other values not used. Undefined for register instructions (bit 10 is set).

21:18

IndexReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no index register (bit 10 is clear 

and bit 22 is set).

22

IndexReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).

26:23

BaseReg (encoded as Reg1 above)
Undefined for register instructions (bit 10 is set) and for memory instructions with no base register (bit 10 is clear 

and bit 27 is set).

27

BaseReg invalid (0 = valid; 1 = invalid)
Undefined for register instructions (bit 10 is set).

29:28

Instruction identity:

0: SLDT

1: STR

2: LLDT

3: LTR

31:30

Undefined.

Table 27-12.  Format of the VM-Exit Instruction-Information Field as Used for RDRAND and RDSEED

Bit Position(s) Content
2:0

Undefined.

Table 27-11.  Format of the VM-Exit Instruction-Information Field as Used for LLDT, LTR, SLDT, and STR (Contd.)

Bit Position(s) Content