Vol. 3B 22-37

ARCHITECTURE COMPATIBILITY

CS

Selector = F000H

Base = FFFF0000H

Limit = FFFFH

AR = Present, R/W, Accessed

Selector = F000H

Base = FFFF0000H

Limit = FFFFH

AR = Present, R/W, Accessed

Selector = F000H

Base = FFFF0000H

Limit = FFFFH

AR = Present, R/W, Accessed

SS, DS, ES, FS, GS

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W, Accessed

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W, Accessed

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W, Accessed

EDX

00000FxxH  

000n06xxH

3

 000005xxH 

EAX

0

4

0

4

0

4

EBX, ECX, ESI, EDI, EBP, 

ESP

00000000H

00000000H

00000000H

ST0 through ST7

5

Pwr up or Reset: +0.0

FINIT/FNINIT: Unchanged

Pwr up or Reset: +0.0

FINIT/FNINIT: Unchanged

Pwr up or Reset: +0.0

FINIT/FNINIT: Unchanged

x87 FPU Control 

Word

5

Pwr up or Reset: 0040H

FINIT/FNINIT: 037FH

Pwr up or Reset: 0040H

FINIT/FNINIT: 037FH

Pwr up or Reset: 0040H

FINIT/FNINIT: 037FH

x87 FPU Status Word

5

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

x87 FPU Tag Word

5

Pwr up or Reset: 5555H

FINIT/FNINIT: FFFFH

Pwr up or Reset: 5555H

FINIT/FNINIT: FFFFH

Pwr up or Reset: 5555H

FINIT/FNINIT: FFFFH

x87 FPU Data 

Operand and CS Seg. 

Selectors

5

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

Pwr up or Reset: 0000H

FINIT/FNINIT: 0000H

x87 FPU Data 

Operand and Inst. 

Pointers

5

Pwr up or Reset: 

   00000000H

FINIT/FNINIT: 00000000H

Pwr up or Reset: 

   00000000H

FINIT/FNINIT: 00000000H

Pwr up or Reset: 

   00000000H

FINIT/FNINIT: 00000000H

MM0 through MM7

5

Pwr up or Reset:

   0000000000000000H

INIT or FINIT/FNINIT:

   Unchanged

Pentium II and Pentium III 

Processors Only—
Pwr up or Reset:

   0000000000000000H

INIT or FINIT/FNINIT:

   Unchanged

Pentium with MMX Technology 

Only—
Pwr up or Reset:

   0000000000000000H

INIT or FINIT/FNINIT:

   Unchanged

XMM0 through XMM7

Pwr up or Reset: 0H

INIT: Unchanged

If CPUID.01H:SSE is 1 —
Pwr up or Reset: 0H

INIT: Unchanged

NA

MXCSR

Pwr up or Reset: 1F80H

INIT: Unchanged

Pentium III processor only-
Pwr up or Reset: 1F80H

INIT: Unchanged

NA

GDTR, IDTR

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

LDTR, Task Register

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

Selector = 0000H

Base = 00000000H

Limit = FFFFH

AR = Present, R/W

DR0, DR1, DR2, DR3

00000000H

00000000H

00000000H

DR6

FFFF0FF0H

FFFF0FF0H

FFFF0FF0H

Table 22-10.  Processor State Following Power-up/Reset/INIT for Pentium, Pentium Pro and Pentium 4 Processors 

Register

Pentium 4 Processor

Pentium Pro Processor

Pentium Processor