MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String

INSTRUCTION SET REFERENCE, M-U

4-108 Vol. 2B

mented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or 
decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

NOTE

To improve performance, more recent processors support modifications to the processor’s 
operation during the string store operations initiated with MOVS and MOVSB. See Section 7.3.9.3 
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for additional 
information on fast-string operation.

The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see “REP/REPE/REPZ 
/REPNE/REPNZ—Repeat String Operation Prefix” for a description of the REP prefix) for block moves of ECX bytes, 
words, or doublewords.
In 64-bit mode, the instruction’s default address size is 64 bits, 32-bit address size is supported using the prefix 
67H. The 64-bit addresses are specified by RSI and RDI; 32-bit address are specified by ESI and EDI. Use of the 
REX.W prefix promotes doubleword operation to 64 bits. See the summary chart at the beginning of this section for 
encoding data and limits.

Operation

DEST ← SRC;

Non-64-bit Mode:

IF (Byte move)

THEN IF DF 

=

 0

THEN 

(E)SI ← (E)SI + 1; 

(E)DI ← (E)DI + 1; 

ELSE 

(E)SI ← (E)SI – 1; 

(E)DI ← (E)DI – 1; 

FI;

ELSE IF (Word move)

THEN IF DF 

= 

0

(E)SI ← (E)SI + 2; 

(E)DI ← (E)DI + 2; 

FI;

ELSE 

(E)SI ← (E)SI – 2; 

(E)DI ← (E)DI – 2; 

FI;

ELSE IF (Doubleword move)

THEN IF DF 

=

 0

(E)SI ← (E)SI + 4; 

(E)DI ← (E)DI + 4; 

FI;

ELSE 

(E)SI ← (E)SI – 4; 

(E)DI ← (E)DI – 4; 

FI;

FI;
64-bit Mode:

IF (Byte move)

THEN IF DF 

=

 0

THEN