DIVSS—Divide Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Vol. 2A 3-295
DIVSS—Divide Scalar Single-Precision Floating-Point Values
Instruction Operand Encoding
Description
Divides the low single-precision floating-point value in the first source operand by the low single-precision floating-
point value in the second source operand, and stores the single-precision floating-point result in the destination
operand. The second source operand can be an XMM register or a 32-bit memory location.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order
doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the
destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword
elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.
Opcode/
Instruction
Op /
En
64/32
bit Mode
Support
CPUID
Feature
Flag
Description
F3 0F 5E /r
DIVSS xmm1, xmm2/m32
RM
V/V
SSE
Divide low single-precision floating-point value in
xmm1 by low single-precision floating-point value in
xmm2/m32.
VEX.NDS.128.F3.0F.WIG 5E /r
VDIVSS xmm1, xmm2, xmm3/m32
RVM
V/V
AVX
Divide low single-precision floating-point value in
xmm2 by low single-precision floating-point value in
xmm3/m32.
EVEX.NDS.LIG.F3.0F.W0 5E /r
VDIVSS xmm1 {k1}{z}, xmm2,
xmm3/m32{er}
T1S
V/V
AVX512F
Divide low single-precision floating-point value in
xmm2 by low single-precision floating-point value in
xmm3/m32.
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA