CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers

INSTRUCTION SET REFERENCE, A-L

3-264 Vol. 2A

CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to 

Packed Doubleword Integers

Instruction Operand Encoding

Description

Converts two, four or eight packed double-precision floating-point values in the source operand (second operand) 
to two, four or eight packed signed doubleword integers in the destination operand (first operand). 
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than 
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is 
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or 
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a 
YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of 
the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination 
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are 
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are 
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are 
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

66 0F E6 /r

CVTTPD2DQ xmm1, xmm2/m128

RM

V/V

SSE2

Convert two packed double-precision floating-point 

values in xmm2/mem to two signed doubleword 

integers in xmm1 using truncation.

VEX.128.66.0F.WIG E6 /r

VCVTTPD2DQ xmm1, xmm2/m128

RM

V/V

AVX

Convert two packed double-precision floating-point 

values in xmm2/mem to two signed doubleword 

integers in xmm1 using truncation.

VEX.256.66.0F.WIG E6 /r

VCVTTPD2DQ xmm1, ymm2/m256

RM

V/V

AVX

Convert four packed double-precision floating-point 

values in ymm2/mem to four signed doubleword 

integers in xmm1 using truncation.

EVEX.128.66.0F.W1 E6 /r

VCVTTPD2DQ xmm1 {k1}{z}, 

xmm2/m128/m64bcst

FV

V/V

AVX512VL

AVX512F

Convert two packed double-precision floating-point 

values in xmm2/m128/m64bcst to two signed 

doubleword integers in xmm1 using truncation subject 

to writemask k1.

EVEX.256.66.0F.W1 E6 /r

VCVTTPD2DQ xmm1 {k1}{z}, 

ymm2/m256/m64bcst

FV

V/V

AVX512VL

AVX512F

Convert four packed double-precision floating-point 

values in ymm2/m256/m64bcst to four signed 

doubleword integers in xmm1 using truncation subject 

to writemask k1.

EVEX.512.66.0F.W1 E6 /r

VCVTTPD2DQ ymm1 {k1}{z}, 

zmm2/m512/m64bcst{sae}

FV

V/V

AVX512F

Convert eight packed double-precision floating-point 

values in zmm2/m512/m64bcst to eight signed 

doubleword integers in ymm1 using truncation subject 

to writemask k1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA