CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value

INSTRUCTION SET REFERENCE, A-L

3-260 Vol. 2A

CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision 

Floating-Point Value

Instruction Operand Encoding

Description

Converts a single-precision floating-point value in the “convert-from” source operand to a double-precision 
floating-point value in the destination operand. When the “convert-from” source operand is an XMM register, the 
single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the 
low quadword of the destination operand.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or 
memory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destina-
tion operand is an XMM register. 
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM 
register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of 
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter 
unpredictable behavior across different processor generations.

Operation

VCVTSS2SD (EVEX encoded version)
IF k1[0] or *no writemask*

THEN

DEST[63:0]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*
ELSE ; 

zeroing-masking

THEN DEST[63:0] = 0

FI;

FI;
DEST[127:64]  SRC1[127:64]
DEST[MAX_VL-1:128]  0

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

F3 0F 5A /r

CVTSS2SD xmm1, xmm2/m32

RM

V/V

SSE2

Convert one single-precision floating-point value in 

xmm2/m32 to one double-precision floating-point value 

in xmm1.

VEX.NDS.128.F3.0F.WIG 5A /r

VCVTSS2SD xmm1, xmm2, 

xmm3/m32

RVM

V/V

AVX

Convert one single-precision floating-point value in 

xmm3/m32 to one double-precision floating-point value 

and merge with high bits of xmm2.

EVEX.NDS.LIG.F3.0F.W0 5A /r

VCVTSS2SD xmm1 {k1}{z}, xmm2, 

xmm3/m32{sae}

T1S

V/V

AVX512F

Convert one single-precision floating-point value in 

xmm3/m32 to one double-precision floating-point value 

and merge with high bits of xmm2 under writemask k1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

RVM

ModRM:reg (w)

VEX.vvvv

ModRM:r/m (r)

NA

T1S

ModRM:reg (w)

EVEX.vvvv

ModRM:r/m (r)

NA