CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value

INSTRUCTION SET REFERENCE, A-L

3-258 Vol. 2A

CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value

Instruction Operand Encoding

Description

Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from” 
source operand to a single-precision floating-point value in the destination operand (first operand). The “convert-
from” source operand can be a general-purpose register or a memory location. The destination operand is an XMM 
register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords 
are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control 
bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input 
value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location. 
Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a general-
purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32) 
of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the 
writemask.
Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter 
unpredictable behavior across different processor generations.

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

F3 0F 2A /r

CVTSI2SS xmm1, r/m32

RM

V/V

SSE

Convert one signed doubleword integer from r/m32 

to one single-precision floating-point value in xmm1.

F3 REX.W 0F 2A /r

CVTSI2SS xmm1, r/m64

RM

V/N.E.

SSE

Convert one signed quadword integer from r/m64 

to one single-precision floating-point value in xmm1.

VEX.NDS.128.F3.0F.W0 2A /r

VCVTSI2SS xmm1, xmm2, r/m32

RVM

V/V

AVX

Convert one signed doubleword integer from r/m32 

to one single-precision floating-point value in xmm1.

VEX.NDS.128.F3.0F.W1 2A /r

VCVTSI2SS xmm1, xmm2, r/m64

RVM

V/N.E.

1

AVX

Convert one signed quadword integer from r/m64 

to one single-precision floating-point value in xmm1.

EVEX.NDS.LIG.F3.0F.W0 2A /r

VCVTSI2SS xmm1, xmm2, r/m32{er}

T1S

V/V

AVX512F

Convert one signed doubleword integer from r/m32 

to one single-precision floating-point value in xmm1.

EVEX.NDS.LIG.F3.0F.W1 2A /r

VCVTSI2SS xmm1, xmm2, r/m64{er}

T1S

V/N.E.

1

NOTES:

1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

AVX512F

Convert one signed quadword integer from r/m64 

to one single-precision floating-point value in xmm1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

RVM

ModRM:reg (w)

VEX.vvvv

ModRM:r/m (r)

NA

T1S

ModRM:reg (w)

EVEX.vvvv

ModRM:r/m (r)

NA