CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers

INSTRUCTION SET REFERENCE, A-L

3-234 Vol. 2A

CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword 

Integers

Instruction Operand Encoding

Description

Converts packed double-precision floating-point values in the source operand (second operand) to packed signed 
doubleword integers in the destination operand (first operand). 
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR 
register or the embedded rounding control bits. If a converted result cannot be represented in the destination 
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value 
(2

w-1

, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit 
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-
tionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are 
zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination 
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are 
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are 
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits 
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified. 
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Opcode

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

F2 0F E6 /r

CVTPD2DQ xmm1, xmm2/m128

RM

V/V

SSE2

Convert two packed double-precision floating-point 

values in xmm2/mem to two signed doubleword 

integers in xmm1.

VEX.128.F2.0F.WIG E6 /r

VCVTPD2DQ xmm1, xmm2/m128

RM

V/V

AVX

Convert two packed double-precision floating-point 

values in xmm2/mem to two signed doubleword 

integers in xmm1.

VEX.256.F2.0F.WIG E6 /r

VCVTPD2DQ xmm1, ymm2/m256

RM

V/V

AVX

Convert four packed double-precision floating-point 

values in ymm2/mem to four signed doubleword 

integers in xmm1.

EVEX.128.F2.0F.W1 E6 /r

VCVTPD2DQ xmm1 {k1}{z}, 

xmm2/m128/m64bcst

FV

V/V

AVX512VL

AVX512F

Convert two packed double-precision floating-point 

values in xmm2/m128/m64bcst to two signed 

doubleword integers in xmm1 subject to writemask k1.

EVEX.256.F2.0F.W1 E6 /r

VCVTPD2DQ xmm1 {k1}{z}, 

ymm2/m256/m64bcst

FV

V/V

AVX512VL

AVX512F

Convert four packed double-precision floating-point 

values in ymm2/m256/m64bcst to four signed 

doubleword integers in xmm1 subject to writemask k1.

EVEX.512.F2.0F.W1 E6 /r

VCVTPD2DQ ymm1 {k1}{z}, 

zmm2/m512/m64bcst{er}

FV

V/V

AVX512F

Convert eight packed double-precision floating-point 

values in zmm2/m512/m64bcst to eight signed 

doubleword integers in ymm1 subject to writemask k1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA