CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-231

CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point 

Values

Instruction Operand Encoding

Description

Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen 
packed single-precision floating-point values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a 
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination 
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmod-
ified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Opcode

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

0F 5B /r

CVTDQ2PS xmm1, xmm2/m128

RM

V/V

SSE2

Convert four packed signed doubleword integers from 

xmm2/mem to four packed single-precision floating-

point values in xmm1.

VEX.128.0F.WIG 5B /r

VCVTDQ2PS xmm1, xmm2/m128

RM

V/V

AVX

Convert four packed signed doubleword integers from 

xmm2/mem to four packed single-precision floating-

point values in xmm1.

VEX.256.0F.WIG 5B /r

VCVTDQ2PS ymm1, ymm2/m256

RM

V/V

AVX

Convert eight packed signed doubleword integers from 

ymm2/mem to eight packed single-precision floating-

point values in ymm1.

EVEX.128.0F.W0 5B /r

VCVTDQ2PS xmm1 {k1}{z}, 

xmm2/m128/m32bcst

FV

V/V

AVX512VL

AVX512F

Convert four packed signed doubleword integers from 

xmm2/m128/m32bcst to four packed single-precision 

floating-point values in xmm1with writemask k1.

EVEX.256.0F.W0 5B /r

VCVTDQ2PS ymm1 {k1}{z}, 

ymm2/m256/m32bcst

FV

V/V

AVX512VL

AVX512F

Convert eight packed signed doubleword integers from 

ymm2/m256/m32bcst to eight packed single-precision 

floating-point values in ymm1with writemask k1.

EVEX.512.0F.W0 5B /r

VCVTDQ2PS zmm1 {k1}{z}, 

zmm2/m512/m32bcst{er}

FV

V/V

AVX512F

Convert sixteen packed signed doubleword integers 

from zmm2/m512/m32bcst to sixteen packed single-

precision floating-point values in zmm1with writemask 

k1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA