CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-227

CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point 

Values

Instruction Operand Encoding

Description

Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two, 
four or eight packed double-precision floating-point values in the destination operand (the first operand). 
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit 
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand 
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with 
EVEX embedded rounding is ignored.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination 
operand is a YMM register. 
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination 
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are 
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination 
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are 
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

F3 0F E6 /r

CVTDQ2PD xmm1, xmm2/m64

RM

V/V

SSE2

Convert two packed signed doubleword integers from 

xmm2/mem to two packed double-precision floating-

point values in xmm1.

VEX.128.F3.0F.WIG E6 /r

VCVTDQ2PD xmm1, xmm2/m64

RM

V/V

AVX

Convert two packed signed doubleword integers from 

xmm2/mem to two packed double-precision floating-

point values in xmm1.

VEX.256.F3.0F.WIG E6 /r

VCVTDQ2PD ymm1, xmm2/m128

RM

V/V

AVX

Convert four packed signed doubleword integers from 

xmm2/mem to four packed double-precision floating-

point values in ymm1.

EVEX.128.F3.0F.W0 E6 /r

VCVTDQ2PD xmm1 {k1}{z}, 

xmm2/m128/m32bcst 

HV

V/V

AVX512VL

AVX512F

Convert 2 packed signed doubleword integers from 

xmm2/m128/m32bcst to eight packed double-precision 

floating-point values in xmm1 with writemask k1.

EVEX.256.F3.0F.W0 E6 /r

VCVTDQ2PD ymm1 {k1}{z}, 

xmm2/m128/m32bcst 

HV

V/V

AVX512VL

AVX512F

Convert 4 packed signed doubleword integers from 

xmm2/m128/m32bcst to 4 packed double-precision 

floating-point values in ymm1 with writemask k1.

EVEX.512.F3.0F.W0 E6 /r

VCVTDQ2PD zmm1 {k1}{z}, 

ymm2/m256/m32bcst 

HV

V/V

AVX512F

Convert eight packed signed doubleword integers from 

ymm2/m256/m32bcst to eight packed double-precision 

floating-point values in zmm1 with writemask k1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

HV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA