CPUID—CPU Identification

INSTRUCTION SET REFERENCE, A-L

3-210 Vol. 2A

Table 3-12.  Encoding of CPUID Leaf 2 Descriptors 

 Value

Type

Description

00H

General

Null descriptor, this byte contains no information

01H

TLB

Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries

02H

TLB

Instruction TLB: 4 MByte pages, fully associative, 2 entries

03H

TLB

Data TLB: 4 KByte pages, 4-way set associative, 64 entries

04H

TLB

Data TLB: 4 MByte pages, 4-way set associative, 8 entries

05H

TLB

Data TLB1: 4 MByte pages, 4-way set associative, 32 entries

06H

Cache

1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size

08H

Cache

1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size

09H

Cache

1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size

0AH

Cache

1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size

0BH

TLB

Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries

0CH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size

0DH

Cache

1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size

0EH

Cache

1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size

1DH

Cache

2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size

21H

Cache

2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size

22H

Cache

3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector

23H

Cache

3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

24H

Cache

2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size

25H

Cache

3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

29H

Cache

3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector

2CH

Cache

1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size

30H

Cache

1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size

40H

Cache

No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

41H

Cache

2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size

42H

Cache

2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size

43H

Cache

2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size

44H

Cache

2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size

45H

Cache

2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size

46H

Cache

3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size

47H

Cache

3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size

48H

Cache

2nd-level cache: 3MByte, 12-way set associative, 64 byte line size

49H

Cache

3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 

06H);
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size

4AH

Cache

3rd-level cache: 6MByte, 12-way set associative, 64 byte line size

4BH

Cache

3rd-level cache: 8MByte, 16-way set associative, 64 byte line size

4CH

Cache

3rd-level cache: 12MByte, 12-way set associative, 64 byte line size

4DH

Cache

3rd-level cache: 16MByte, 16-way set associative, 64 byte line size

4EH

Cache

2nd-level cache: 6MByte, 24-way set associative, 64 byte line size

4FH 

TLB

Instruction TLB: 4 KByte pages, 32 entries