CPUID—CPU Identification

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-199

Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)

14H

NOTES:

Leaf 14H main leaf (ECX = 0). 

EAX

Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.

EBX

Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH 

MSR can be accessed.

Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.

Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across 

warm reset.

Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.

Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and 

IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.

Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn), 

enabling Power Event Trace packet generation.

Bit 31 - 06: Reserved. 

ECX

Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output 

scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.

Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the Mas-

kOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.

Bit 02: If 1, indicates support of Single-Range Output scheme.

Bit 03: If 1, indicates support of output to Trace Transport subsystem.

Bit 30 - 04: Reserved.

Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-

ponent.

EDX

Bits 31 - 00: Reserved.

Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)

14H

EAX

Bits 02 - 00: Number of configurable Address Ranges for filtering.

Bits 15 - 03: Reserved.

Bits 31 - 16: Bitmap of supported MTC period encodings.

EBX

Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings.

Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.

ECX

Bits 31 - 00: Reserved.

EDX 

Bits 31 - 00: Reserved.

Time Stamp Counter/Core Crystal Clock Information-leaf 

15H

NOTES:

If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
“TSC frequency” = “core crystal clock frequency” * EBX/EAX.

The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.

EAX

Bits 31 - 00: An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio.

EBX

Bits 31 - 00: An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio.

ECX

Bits 31 - 00: Reserved = 0.

EDX

Bits 31 - 00: Reserved = 0.

Table 3-8.  Information Returned by CPUID Instruction (Contd.)

Initial EAX 

Value

Information Provided about the Processor