CPUID—CPU Identification

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-195

** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this 

field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors 

available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software 

and platform hardware configurations. 

*** The value of the “level type” field is not related to level numbers in any way, higher “level type” val-

ues do not mean higher levels. Level type field has the following encoding:

0: Invalid.

1: SMT.

2: Core.

3-255: Reserved.

Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)

0DH

NOTES:

Leaf 0DH main leaf (ECX = 0). 

EAX

Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if 

EAX[n] is 1.

Bit 00: x87 state. 

Bit 01: SSE state.

Bit 02: AVX state.

Bits 04 - 03: MPX state.

Bits 07 - 05: AVX-512 state.

Bit 08: Used for IA32_XSS.

Bit 09: PKRU state.

Bits 31 - 10: Reserved.

EBX

Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by 

enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area 

are not enabled.

ECX

Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the 

XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in 

XCR0. 

EDX

Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if 

EDX[n] is 1.

Bits 31 - 00: Reserved.

Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)

0DH

EAX

Bit 00: XSAVEOPT is available.

Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.

Bit 02: Supports XGETBV with ECX = 1 if set.

Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.

Bits 31 - 04: Reserved.

EBX

Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.

ECX

Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be 

set to 1 only if ECX[n] is 1.

Bits 07 - 00: Used for XCR0.

Bit 08: PT state.

Bit 09: Used for XCR0.

Bits 31 - 10: Reserved.

EDX 

Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can 

be set to 1 only if EDX[n] is 1.

Bits 31 - 00: Reserved.

Table 3-8.  Information Returned by CPUID Instruction (Contd.)

Initial EAX 

Value

Information Provided about the Processor