COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS

INSTRUCTION SET REFERENCE, A-L

Vol. 2A 3-187

COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS

Instruction Operand Encoding

Description

Compares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand 
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, 
greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result 
is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location. 
The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-
tion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid 
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter 
unpredictable behavior across different processor generations.

Operation

COMISS (all versions)
RESULT OrderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF

UNORDERED: ZF,PF,CF  111;
GREATER_THAN: ZF,PF,CF  000;
LESS_THAN: ZF,PF,CF  001;
EQUAL: ZF,PF,CF  100;

ESAC;
OF, AF, SF  0; }

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

0F 2F /r

COMISS xmm1, xmm2/m32

RM

V/V

SSE

Compare low single-precision floating-point values in 

xmm1 and xmm2/mem32 and set the EFLAGS flags 

accordingly.

VEX.128.0F.WIG 2F /r

VCOMISS xmm1, xmm2/m32

RM

V/V

AVX

Compare low single-precision floating-point values in 

xmm1 and xmm2/mem32 and set the EFLAGS flags 

accordingly.

EVEX.LIG.0F.W0 2F /r

VCOMISS xmm1, xmm2/m32{sae}

T1S

V/V

AVX512F

Compare low single-precision floating-point values in 

xmm1 and xmm2/mem32 and set the EFLAGS flags 

accordingly.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

NA

NA

T1S

ModRM:reg (w)

ModRM:r/m (r)

NA

NA