CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes

INSTRUCTION SET REFERENCE, A-L

3-182 Vol. 2A

CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes

Instruction Operand Encoding

Description

Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand 
(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored 
in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX). 
The destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For 
the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the 
low-order 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-
order 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value. 
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the 
interface to the processor’s bus, the destination operand receives a write cycle without regard to the result of the 
comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is 
written into the destination. (The processor never produces a locked read without also producing a locked write.)
In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that 
CMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the 
beginning of this section for encoding data and limits. For information on the CPUID flag that indicates 
CMPXCHG16B, see page 3-205

.

IA-32 Architecture Compatibility

This instruction encoding is not supported on Intel processors earlier than the Pentium processors.

Opcode/

Instruction

Op/ 

En

64-Bit 

Mode

Compat/

Leg Mode

Description

0F C7 /1 m64
CMPXCHG8B m64

M

Valid

Valid*

Compare EDX:EAX with m64. If equal, set ZF and load 

ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.

REX.W + 0F C7 /1 m128
CMPXCHG16B m128

M

Valid

N.E.

Compare RDX:RAX with m128. If equal, set ZF and load 

RCX:RBX into m128. Else, clear ZF and load m128 into 

RDX:RAX.

NOTES:

*See IA-32 Architecture Compatibility section below.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (r, w)

NA

NA

NA