XSAVEC—Save Processor Extended States with Compaction

INSTRUCTION SET REFERENCE, V-Z

Vol. 2C 5-575

XSAVEC—Save Processor Extended States with Compaction

Instruction Operand Encoding

Description

Performs a full or partial save of processor state components to the XSAVE area located at the memory address 
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The 
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the 
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1.
Section 13.10, “Operation of XSAVEC,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 
1 provides a detailed description of the operation of the XSAVEC instruction. The following items provide a high-
level outline:

•

Execution of XSAVEC is similar to that of XSAVE. XSAVEC differs from XSAVE in that it uses compaction and that 
it may use the init optimization.

•

XSAVEC saves state component i if and only if RFBM[i] =  1  and  XINUSE[i] =  1.

1

 (XINUSE is a bitmap by which 

the processor tracks the status of various state components. See Section 13.6, “Processor Tracking of XSAVE-
Managed State.”)

•

XSAVEC does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, “Legacy 
Region of an XSAVE Area”).

•

XSAVEC writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.

2,3

 (See 

Section 13.4.2, “XSAVE Header.”) XSAVEC sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to 
RFBM[62:0]. XSAVEC does not write to any parts of the XSAVE header other than the XSTATE_BV and 
XCOMP_BV fields.

•

XSAVEC always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3, 
“Extended Region of an XSAVE Area”).

Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a 
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.

Operation

RFBM ← XCR0 AND EDX:EAX; /* bitwise logical AND */

COMPMASK ← RFBM OR 80000000_00000000H;

IF RFBM[0] = 1 and XINUSE[0] = 1

Opcode

Instruction

Op/ 

En

64-Bit 

Mode

Compat/

Leg Mode

Description

0F C7 /4

XSAVEC mem

M

Valid

Valid

Save state components specified by EDX:EAX 

to mem with compaction.

REX.W+ 0F C7 /4

XSAVEC64 mem

M

Valid

N.E.

Save state components specified by EDX:EAX 

to mem with compaction.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m  (w)

NA

NA

NA

1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not 

have its initial value of 1F80H. In this case, XSAVEC saves SSE state as long as RFBM[1] = 1.

2. Unlike XSAVE and XSAVEOPT, XSAVEC clears bits in the XSTATE_BV field that correspond to bits that are clear in RFBM.
3. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not 

have its initial value of 1F80H. In this case, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.