VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with

INSTRUCTION SET REFERENCE, V-Z

5-514 Vol. 2C

VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch 

Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent 

to Write

Instruction Operand Encoding

Description

The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The 
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only 
be prefetched if their corresponding mask bit is one. 
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):
• T0 (temporal data)—prefetch data into the first level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations. 
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation

BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by ‘mem’ into the cache level specified by ‘Level’; a request 

for exclusive/ownership is done if ‘State’ is 1. Note that the memory location ignore cache line splits. This operation is considered a 

hint for the processor and may be skipped depending on implementation.

Opcode/

Instruction

Op/

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.512.66.0F38.W0 C6 /5 /vsib 

T1S

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte 

memory locations containing single-precision data using 

writemask k1 and T0 hint with intent to write.

VSCATTERPF0DPS vm32z {k1}

EVEX.512.66.0F38.W0 C7 /5 /vsib 

T1S

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte 

memory locations containing single-precision data using 

writemask k1 and T0 hint with intent to write.

VSCATTERPF0QPS vm64z {k1}

EVEX.512.66.0F38.W1 C6 /5 /vsib 

T1S

V/V

AVX512PF

Using signed dword indices, prefetch sparse byte 

memory locations containing double-precision data 

using writemask k1 and T0 hint with intent to write.

VSCATTERPF0DPD vm32y {k1}

EVEX.512.66.0F38.W1 C7 /5 /vsib 

T1S

V/V

AVX512PF

Using signed qword indices, prefetch sparse byte 

memory locations containing double-precision data 

using writemask k1 and T0 hint with intent to write.

VSCATTERPF0QPD vm64z {k1}

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

T1S

BaseReg (R): VSIB:base,

VectorReg(R): VSIB:index

NA

NA

NA