VMASKMOV—Conditional SIMD Packed Loads and Stores

INSTRUCTION SET REFERENCE, V-Z

Vol. 2C 5-289

VMASKMOV—Conditional SIMD Packed Loads and Stores

Instruction Operand Encoding

Description

Conditionally moves packed data elements from the second source operand into the corresponding data element 
of the destination operand, depending on the mask bits associated with each data element. The mask bits are 
specified in the first source operand. 
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask 
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the 
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in 
the store form. 
The second source operand is a memory address for the load form of these instruction. The destination operand is 
a memory address for the store form of these instructions. The other operands are both XMM registers (for 
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to 
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no 
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to 
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits 
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the 
ordering of the individual loads or stores it does is implementation specific. 

Opcode/

Instruction

Op/ 

En

64/32-bit 

Mode

CPUID 

Feature 

Flag

Description

VEX.NDS.128.66.0F38.W0 2C /r
VMASKMOVPS xmm1, xmm2, m128

RVM V/V

AVX

Conditionally load packed single-precision values from 

m128 using mask in xmm2 and store in xmm1.

VEX.NDS.256.66.0F38.W0 2C /r
VMASKMOVPS ymm1, ymm2, m256

RVM V/V

AVX

Conditionally load packed single-precision values from 

m256 using mask in ymm2 and store in ymm1.

VEX.NDS.128.66.0F38.W0 2D /r
VMASKMOVPD xmm1, xmm2, m128

RVM V/V

AVX

Conditionally load packed double-precision values from 

m128 using mask in xmm2 and store in xmm1.

VEX.NDS.256.66.0F38.W0 2D /r
VMASKMOVPD ymm1, ymm2, m256

RVM V/V

AVX

Conditionally load packed double-precision values from 

m256 using mask in ymm2 and store in ymm1.

VEX.NDS.128.66.0F38.W0 2E /r
VMASKMOVPS m128, xmm1, xmm2

MVR V/V

AVX

Conditionally store packed single-precision values from 

xmm2 using mask in xmm1.

VEX.NDS.256.66.0F38.W0 2E /r
VMASKMOVPS m256, ymm1, ymm2

MVR V/V

AVX

Conditionally store packed single-precision values from 

ymm2 using mask in ymm1.

VEX.NDS.128.66.0F38.W0 2F /r
VMASKMOVPD m128, xmm1, xmm2

MVR V/V

AVX

Conditionally store packed double-precision values from 

xmm2 using mask in xmm1.

VEX.NDS.256.66.0F38.W0 2F /r
VMASKMOVPD m256, ymm1, ymm2

MVR V/V

AVX

Conditionally store packed double-precision values from 

ymm2 using mask in ymm1.

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

NA

MVR

ModRM:r/m (w)

VEX.vvvv (r)

ModRM:reg (r)

NA