VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, V-Z

Vol. 2C 5-71

VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision 

Floating-Point Values

Instruction Operand Encoding

Description

Converts packed unsigned quadword integers in the source operand (second operand) to single-precision floating-
point values in the destination operand (first operand). 
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. 
The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. 
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTUQQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) 

THEN

SET_RM(EVEX.RC);

ELSE 

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 32
k  j * 64
IF k1[j] OR *no writemask*

THEN DEST[i+31:i] 

Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*
ELSE ; 

zeroing-masking

DEST[i+31:i]  0

FI

FI;

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.128.F2.0F.W1 7A /r

FV

V/V

AVX512VL

Convert two packed unsigned quadword integers from 

xmm2/m128/m64bcst to packed single-precision floating-

point values in zmm1 with writemask k1.

VCVTUQQ2PS xmm1 {k1}{z}, 

xmm2/m128/m64bcst 

AVX512DQ

EVEX.256.F2.0F.W1 7A /r

FV

V/V

AVX512VL

Convert four packed unsigned quadword integers from 

ymm2/m256/m64bcst to packed single-precision floating-

point values in xmm1 with writemask k1.

VCVTUQQ2PS xmm1 {k1}{z}, 

ymm2/m256/m64bcst 

AVX512DQ

EVEX.512.F2.0F.W1 7A /r

FV

V/V

AVX512DQ

Convert eight packed unsigned quadword integers from 

zmm2/m512/m64bcst to eight packed single-precision 

floating-point values in zmm1 with writemask k1.

VCVTUQQ2PS ymm1 {k1}{z}, 

zmm2/m512/m64bcst{er}

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA