VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values

INSTRUCTION SET REFERENCE, V-Z

5-58 Vol. 2C

VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to 

Packed Singed Quadword Integer Values

Instruction Operand Encoding

Description

Converts with truncation packed single-precision floating-point values in the source operand to eight signed quad-
word integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR 
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception 
is raised, and if this exception is masked, the indefinite integer value (2

w-1

, where w represents the number of bits 

in the destination format) is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit 
memory location. The destination operation is a vector register conditionally updated with writemask k1. 
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1

i  j * 64
k  j * 32
IF k1[j] OR *no writemask*

THEN DEST[i+63:i] 

Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*
ELSE ; 

zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR
DEST[MAX_VL-1:VL]  0

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.128.66.0F.W0 7A /r

HV

V/V

AVX512VL

Convert two packed single precision floating-point values from 

xmm2/m64/m32bcst to two packed signed quadword values in 

xmm1 using truncation subject to writemask k1.

VCVTTPS2QQ xmm1 {k1}{z}, 

xmm2/m64/m32bcst

AVX512DQ

EVEX.256.66.0F.W0 7A /r

HV

V/V

AVX512VL

Convert four packed single precision floating-point values from 

xmm2/m128/m32bcst to four packed signed quadword values 

in ymm1 using truncation subject to writemask k1.

VCVTTPS2QQ ymm1 {k1}{z}, 

xmm2/m128/m32bcst

AVX512DQ

EVEX.512.66.0F.W0 7A /r

HV

V/V

AVX512DQ

Convert eight packed single precision floating-point values from 

ymm2/m256/m32bcst to eight packed signed quadword values 

in zmm1 using truncation subject to writemask k1.

VCVTTPS2QQ zmm1 {k1}{z}, 

ymm2/m256/m32bcst{sae}

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

HV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA