VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers

INSTRUCTION SET REFERENCE, V-Z

5-50 Vol. 2C

VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to 

Packed Quadword Integers

Instruction Operand Encoding

Description

Converts with truncation packed double-precision floating-point values in the source operand (second operand) to 
packed quadword integers in the destination operand (first operand). 
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. 
The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. 
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR 
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception 
is raised, and if this exception is masked, the indefinite integer value (2

w-1

, where w represents the number of bits 

in the destination format) is returned.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1

i  j * 64
IF k1[j] OR *no writemask*

THEN DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*
ELSE ; 

zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR
DEST[MAX_VL-1:VL]  0

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.128.66.0F.W1 7A /r

FV

V/V

AVX512VL

Convert two packed double-precision floating-point values from 

zmm2/m128/m64bcst to two packed quadword integers in 

zmm1 using truncation with writemask k1.

VCVTTPD2QQ xmm1 {k1}{z}, 

xmm2/m128/m64bcst

AVX512DQ

EVEX.256.66.0F.W1 7A /r

FV

V/V

AVX512VL

Convert four packed double-precision floating-point values 

from ymm2/m256/m64bcst to four packed quadword integers 

in ymm1 using truncation with writemask k1.

VCVTTPD2QQ ymm1 {k1}{z}, 

ymm2/m256/m64bcst

AVX512DQ

EVEX.512.66.0F.W1 7A /r

FV

V/V

AVX512DQ

Convert eight packed double-precision floating-point values 

from zmm2/m512 to eight packed quadword integers in zmm1 

using truncation with writemask k1.

VCVTTPD2QQ zmm1 {k1}{z}, 

zmm2/m512/m64bcst{sae}

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA