VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, V-Z

5-44 Vol. 2C

VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point 

Values

Instruction Operand Encoding

Description

Converts packed quadword integers in the source operand (second operand) to packed single-precision floating-
point values in the destination operand (first operand). 
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation 
is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1. 
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTQQ2PS (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64
k  j * 32
IF k1[j] OR *no writemask*

THEN DEST[k+31:k] 

Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[k+31:k] remains unchanged*
ELSE ; 

zeroing-masking

DEST[k+31:k]  0

FI

FI;

ENDFOR
DEST[MAX_VL-1:VL/2]  0

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.128.0F.W1 5B /r

FV

V/V

AVX512VL

Convert two packed quadword integers from xmm2/mem to 

packed single-precision floating-point values in xmm1 with 

writemask k1.

VCVTQQ2PS xmm1 {k1}{z}, 

xmm2/m128/m64bcst 

AVX512DQ

EVEX.256.0F.W1 5B /r

FV

V/V

AVX512VL

Convert four packed quadword integers from ymm2/mem to 

packed single-precision floating-point values in xmm1 with 

writemask k1.

VCVTQQ2PS xmm1 {k1}{z}, 

ymm2/m256/m64bcst 

AVX512DQ

EVEX.512.0F.W1 5B /r

FV

V/V

AVX512DQ

Convert eight packed quadword integers from zmm2/mem to 

eight packed single-precision floating-point values in ymm1 with 

writemask k1.

VCVTQQ2PS ymm1 {k1}{z}, 

zmm2/m512/m64bcst{er} 

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

FV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA