VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V-Z
5-42 Vol. 2C
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point
Values
Instruction Operand Encoding
Description
Converts packed quadword integers in the source operand (second operand) to packed double-precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PD (EVEX2 encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j 0 TO KL-1
i j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE ;
zeroing-masking
DEST[i+63:i] 0
FI
FI;
ENDFOR
Opcode/
Instruction
Op /
En
64/32
bit Mode
Support
CPUID
Feature
Flag
Description
EVEX.128.F3.0F.W1 E6 /r
FV
V/V
AVX512VL
Convert two packed quadword integers from
xmm2/m128/m64bcst to packed double-precision floating-
point values in xmm1 with writemask k1.
VCVTQQ2PD xmm1 {k1}{z},
xmm2/m128/m64bcst
AVX512DQ
EVEX.256.F3.0F.W1 E6 /r
FV
V/V
AVX512VL
Convert four packed quadword integers from
ymm2/m256/m64bcst to packed double-precision floating-
point values in ymm1 with writemask k1.
VCVTQQ2PD ymm1 {k1}{z},
ymm2/m256/m64bcst
AVX512DQ
EVEX.512.F3.0F.W1 E6 /r
FV
V/V
AVX512DQ
Convert eight packed quadword integers from
zmm2/m512/m64bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
VCVTQQ2PD zmm1 {k1}{z},
zmm2/m512/m64bcst{er}
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA