VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values

INSTRUCTION SET REFERENCE, V-Z

5-40 Vol. 2C

VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned 

Quadword Integer Values

Instruction Operand Encoding

Description

Converts up to eight packed single-precision floating-point values in the source operand to unsigned quadword 
integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR 
register or the embedded rounding control bits. If a converted result cannot be represented in the destination 
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2

w

 – 1 is 

returned, where w represents the number of bits in the destination format.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1. 
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1) 

THEN

SET_RM(EVEX.RC);

ELSE 

SET_RM(MXCSR.RM);

FI;
FOR j  0 TO KL-1

i  j * 64
k  j * 32
IF k1[j] OR *no writemask*

THEN DEST[i+63:i] 

Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])

ELSE 

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*
ELSE ; 

zeroing-masking

Opcode/

Instruction

Op / 

En

64/32 

bit Mode 

Support

CPUID 

Feature 

Flag

Description

EVEX.128.66.0F.W0 79 /r

HV

V/V

AVX512VL

Convert two packed single precision floating-point values from 

zmm2/m64/m32bcst to two packed unsigned quadword values 

in zmm1 subject to writemask k1.

VCVTPS2UQQ xmm1 {k1}{z}, 

xmm2/m64/m32bcst

AVX512DQ

EVEX.256.66.0F.W0 79 /r

HV

V/V

AVX512VL

Convert four packed single precision floating-point values from 

xmm2/m128/m32bcst to four packed unsigned quadword 

values in ymm1 subject to writemask k1.

VCVTPS2UQQ ymm1 {k1}{z}, 

xmm2/m128/m32bcst

AVX512DQ

EVEX.512.66.0F.W0 79 /r

HV

V/V

AVX512DQ

Convert eight packed single precision floating-point values from 

ymm2/m256/m32bcst to eight packed unsigned quadword 

values in zmm1 subject to writemask k1.

VCVTPS2UQQ zmm1 {k1}{z}, 

ymm2/m256/m32bcst{er}

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

HV

ModRM:reg (w)

ModRM:r/m (r)

NA

NA