PSHUFLW—Shuffle Packed Low Words
INSTRUCTION SET REFERENCE, M-U
4-424 Vol. 2B
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
PSHUFLW (128-bit Legacy SSE version)
DEST[15:0] (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VPSHUFLW (VEX.128 encoded version)
DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC[127:64]
DEST[VLMAX-1:128] 0
VPSHUFLW (VEX.256 encoded version)
DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC1[127:64]
DEST[143:128] (SRC1 >> (imm[1:0] *16))[143:128]
DEST[159:144] (SRC1 >> (imm[3:2] * 16))[143:128]
DEST[175:160] (SRC1 >> (imm[5:4] * 16))[143:128]
DEST[191:176] (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] SRC1[255:192]
DEST[VLMAX-1:256] 0
VPSHUFLW (EVEX.U1.512 encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
TMP_DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
TMP_DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
TMP_DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
TMP_DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
TMP_DEST[127:64] SRC1[127:64]
FI;
IF VL >= 256
TMP_DEST[143:128] (SRC1 >> (imm[1:0] *16))[143:128]
TMP_DEST[159:144] (SRC1 >> (imm[3:2] * 16))[143:128]
TMP_DEST[175:160] (SRC1 >> (imm[5:4] * 16))[143:128]
TMP_DEST[191:176] (SRC1 >> (imm[7:6] * 16))[143:128]
TMP_DEST[255:192] SRC1[255:192]
FI;
IF VL >= 512
TMP_DEST[271:256] (SRC1 >> (imm[1:0] *16))[271:256]
TMP_DEST[287:272] (SRC1 >> (imm[3:2] * 16))[271:256]