Vol. 1 4-15

DATA TYPES

normalized number.   Since  −129

10

 is beyond the allowable exponent range, the result is denormalized by inserting 

leading zeros until the minimum exponent of −126

10

 is reached.

In the extreme case, all the significant bits are shifted out to the right by leading zeros, creating a zero result. 
The Intel 64 and IA-32 architectures deal with denormal values in the following ways:

•

It avoids creating denormals by normalizing numbers whenever possible.

•

It provides the floating-point underflow exception to permit programmers to detect cases when denormals are 
created.

•

It provides the floating-point denormal-operand exception to permit procedures or programs to detect when 
denormals are being used as source operands for computations.

4.8.3.3  

Signed Infinities

The two infinities, + ∞ and − ∞, represent the maximum positive and negative real numbers, respectively, that can 

be represented in the floating-point format. Infinity is always represented by a significand of 1.00...00 (the integer 
bit may be implied) and the maximum biased exponent allowed in the specified format (for example, 255

10

 for the 

single-precision format).
The signs of infinities are observed, and comparisons are possible. Infinities are always interpreted in the affine 
sense; that is, –∞ is less than any finite number and +∞ is greater than any finite number. Arithmetic on infinities 

is always exact. Exceptions are generated only when the use of an infinity as a source operand constitutes an 
invalid operation.
Whereas denormalized numbers may represent an underflow condition, the two ∞ numbers may represent the 

result of an overflow condition. Here, the normalized result of a computation has a biased exponent greater than 
the largest allowable exponent for the selected result format.

4.8.3.4  

NaNs

Since NaNs are non-numbers, they are not part of the real number line. In Figure 4-12, the encoding space for 
NaNs in the floating-point formats is shown above the ends of the real number line. This space includes any value 
with the maximum allowable biased exponent and a non-zero fraction (the sign bit is ignored for NaNs).
The IA-32 architecture defines two classes of NaNs: quiet NaNs (QNaNs) and signaling NaNs (SNaNs). A QNaN is a 
NaN with the most significant fraction bit set; an SNaN is a NaN with the most significant fraction bit clear. QNaNs 
are allowed to propagate through most arithmetic operations without signaling an exception. SNaNs generally 
signal a floating-point invalid-operation exception whenever they appear as operands in arithmetic operations.
SNaNs are typically used to trap or invoke an exception handler. They must be inserted by software; that is, the 
processor never generates an SNaN as a result of a floating-point operation.

Table 4-6.  Denormalization Process

Operation

Sign

Exponent*

Significand

True Result

0

−129

1.01011100000...00

Denormalize

0

−128

0.10101110000...00

Denormalize

0

−127

0.01010111000...00

Denormalize

0

−126

0.00101011100...00

Denormal Result

0

−126

0.00101011100...00

* Expressed as an unbiased, decimal number.