17-12 Vol. 1

INTEL® MEMORY PROTECTION EXTENSIONS

VM exits always save IA32_BNDCFGS into BNDCFGS field of VMCS; if “clear BNDCFGS” is 1, VM exits clear 
IA32_BNDCFGS. If “load BNDCFGS” is 1, VM entry loads IA32_BNDCFGS from VMCS. If loading IA32_BNDCFGS, 
VM entry should check the value of that register in the guest-state area of the VMCS and cause the VM entry to fail 
(late) if the value is one that would causes WRMSR to fault if executed in ring 0.

17.5.8 

Support of Intel MPX in Intel TSX

For some processor implementations, the following Intel MPX instructions may always cause transactional aborts:

•

An Intel TSX transaction abort will occur in case of legacy branch (that causes bounds registers INIT) when at 
least one bounds register was in a NON-INIT state.

•

An Intel TSX transaction abort will occur in case of a BNDLDX & BNDSTX instruction on non-flat segment.

Intel MPX Instructions (including BND prefix + branch instructions) not enumerated above as causing transactional 
abort when used inside a transaction will typically not cause an Intel TSX transaction to abort.