16-6 Vol. 1
PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS
16.3.7
RTM-Enabled Debugger Support
Any debug exception (#DB) or breakpoint exception (#BP) inside an RTM region causes a transactional abort and,
by default, redirects control flow to the fallback instruction address with architectural state recovered and bit 4 in
EAX set. However, to allow software debuggers to intercept execution on debug or breakpoint exceptions, the RTM
architecture provides additional capability called advanced debugging of RTM transactional regions.
Advanced debugging of RTM transactional regions is enabled if bit 11 of DR7 and bit 15 of the IA32_DEBUGCTL MSR
are both 1. In this case, any RTM transactional abort due to a #DB or #BP causes execution to roll back to just
before the XBEGIN instruction (EAX is restored to the value it had before XBEGIN) and then delivers a #DB. (A #DB
is delivered even if the transactional abort was caused by a #BP.) DR6[16] is cleared to indicate that the exception
resulted from a debug or breakpoint exception inside an RTM region. See also Section 17.3.3, “Debug Exceptions,
Breakpoint Exceptions, and Restricted Transactional Memory (RTM),” of Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 3B.
16.3.8 Programming
Considerations
Typical programmer-identified regions are expected to execute transactionally and to commit successfully.
However, Intel TSX does not provide any such guarantee. A transactional execution may abort for many reasons.
To take full advantage of the transactional capabilities, programmers should follow certain guidelines to increase
the probability of their transactional execution committing successfully.
This section discusses various events that may cause transactional aborts. The architecture ensures that updates
performed within a transactional region that subsequently aborts execution will never become visible. Only a
committed transactional execution updates architectural state. Transactional aborts never cause functional failures
and only affect performance.
16.3.8.1 Instruction Based Considerations
Programmers can use any instruction safely inside a transactional region. Further, programmers can use the Intel
TSX instructions and prefixes at any privilege level. However, some instructions will always abort the transactional
execution and cause execution to seamlessly and safely transition to a non-transactional path.
Intel TSX allows for most common instructions to be used inside transactional regions without causing aborts. The
following operations inside a transactional region do not typically cause an abort.
•
Operations on the instruction pointer register, general purpose registers (GPRs) and the status flags (CF, OF, SF,
PF, AF, and ZF).
•
Operations on XMM and YMM registers and the MXCSR register
However, programmers must be careful when intermixing SSE and AVX operations inside a transactional region.
Intermixing SSE instructions accessing XMM registers and AVX instructions accessing YMM registers may cause
transactional regions to abort.
CLD and STD instructions when used inside transactional regions may cause aborts if they change the value of the
DF flag. However, if DF is 1, the STD instruction will not cause an abort. Similarly, if DF is 0, the CLD instruction will
not cause an abort.
Instructions not enumerated here as causing abort when used inside a transactional region will typically not cause
the execution to abort (examples include but are not limited to MFENCE, LFENCE, SFENCE, RDTSC, RDTSCP, etc.).
The following instructions will abort transactional execution on any implementation:
•
XABORT
•
CPUID
•
PAUSE
In addition, in some implementations, the following instructions may always cause transactional aborts. These
instructions are not expected to be commonly used inside typical transactional regions. However, programmers
must not rely on these instructions to force a transactional abort, since whether they cause transactional aborts is
implementation dependent.
•
Operations on X87 and MMX architecture state. This includes all MMX and X87 instructions, including the
FXRSTOR and FXSAVE instructions.