7-20 Vol. 1

PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS

When fast-string operation is enabled (because IA32_MISC_ENABLE[0] = 1), some processors may further 
enhance the operation of the REP MOVSB and REP STOSB instructions. A processor supports these enhancements 
if CPUID.(EAX=07H, ECX=0H):EBX[bit 9] is 1. The Intel® 64 and IA-32 Architectures Optimization Reference 
Manual may include model-specific recommendations for use of these enhancements.
The stores produced by fast-string operation may appear to execute out of order. Software dependent upon 
sequential store ordering should not use string operations for the entire data structure to be stored. Data and 
semaphores should be separated. Order-dependent code should write to a discrete semaphore variable after any 
string operations to allow correctly ordered data to be seen by all processors. Atomicity of load and store operations 
is guaranteed only for native data elements of the string with native data size, and only if they are included in a 
single cache line. See Section 8.2.4, “Fast-String Operation and Out-of-Order Stores” of Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3A.

7.3.9.4  

String Operations in 64-Bit Mode

The behavior of MOVS (Move String), CMPS (Compare string), SCAS (Scan string), LODS (Load string), and STOS 
(Store string) instructions in 64-bit mode is similar to their behavior in non-64-bit modes, with the following differ-
ences:

•

The source operand is specified by RSI or DS:ESI, depending on the address size attribute of the operation. 

•

The destination operand is specified by RDI or DS:EDI, depending on the address size attribute of the 
operation. 

•

Operation on 64-bit data is supported by using the REX.W prefix.

When using REP prefixes for string operations in 64-bit mode, the repeat count is specified by RCX or ECX 
(depending on the address size attribute of the operation). The default address size is 64 bits.

7.3.10 I/O 

Instructions

The IN (input from port to register), INS (input from port to string), OUT (output from register to port), and OUTS 
(output string to port) instructions move data between the processor’s I/O ports and either a register or memory.
The register I/O instructions (IN and OUT) move data between an I/O port and the EAX register (32-bit I/O), the 
AX register (16-bit I/O), or the AL (8-bit I/O) register. The I/O port being read or written to is specified with an 
immediate operand or an address in the DX register. 
The block I/O instructions (INS and OUTS) instructions move blocks of data (strings) between an I/O port and 
memory. These instructions operate similar to the string instructions (see Section 7.3.9, “String Operations”). The 
ESI and EDI registers are used to specify string elements in memory and the repeat prefix (REP) is used to repeat 
the instructions to implement block moves. The assembler recognizes the following alternate mnemonics for these 
instructions: INSB (input byte), INSW (input word), and INSD (input doubleword), and OUTSB (output byte), 
OUTSW (output word), and OUTSD (output doubleword).
The INS and OUTS instructions use an address in the DX register to specify the I/O port to be read or written to.

7.3.11 

I/O Instructions in 64-Bit Mode

For I/O instructions to and from memory, the differences in 64-bit mode are:

•

The source operand is specified by RSI or DS:ESI, depending on the address size attribute of the operation. 

•

The destination operand is specified by RDI or DS:EDI, depending on the address size attribute of the 
operation. 

•

Operation on 64-bit data is not encodable and REX prefixes are silently ignored.